1. Field of the Invention
The present invention relates to memory architectures. More particularly, the present invention relates to a circuit and method to increase the read margin in non-volatile memories (NVMs) by using a differential sensing scheme.
2. Background Information
Conventionally, a programmable non-volatile memory (NVM) device is useful in many applications, because they retain programmed information even if power is subsequently isolated from the memory device. Like other types of electronic memories, programmable NVMs are usually constructed as an array of bit cells, with each bit cells storing one bit of information. Unlike other memory types, the bit cells used in many programmable NVMs permit electric charge to be injected into a storage node during programming, with the injected charge remaining in the storage node until the bit cell is erased. For example, if the charge stored in the storage node is of a negative type (e.g., electrons), then the particular cell is called a program cell. If the charge stored in the storage node is of a positive type (e.g., holes), then the particular cell is called an erase cell.
One type of a conventional programmable NVM is a flash memory, which uses a floating-gate bit cell structure. Floating-gate bit cells are transistors that incorporate both a control gate and a floating gate. The control gate is used to properly bias the transistor for reading, programming or erasing data, and the floating gate is used as the storage node for the bit cell. By storing different amounts and types of charge in the floating gate, the amount of voltage needed to bias the transistor into a conduction state, commonly referred to as the voltage threshold (Vt), is altered. It is the voltage threshold of the transistor that determines whether the bit cell represents a 1 to 0.
The floating-gate structure has at least two known limitations. First, floating-gate bit cells require relatively long program and erase times compared to other bit cell types. Second, the voltages needed to inject charge into a floating-gate bit cell require transistors with relatively thick oxide layers. Another undesirable characteristic of floating-gate memories is that a large number of process steps are needed to fabricate floating-gate bit cells. To overcome some of the limitations of floating-gate memories, other NVM architectures have been developed. NVM architecture using silicon-Oxygen-Nitrogen-Oxygen-Silicon (SONOS) memories provide advanced operational features over floating-gate structures. The advantages of simplicity, scalability, thinner tunnel oxide, reduced electric-fields and directly coupled gate voltages are some of the advanced features of NVM architectures using SONOS memories. However, SONOS memories generally exhibit problems related to leakage of stored charge during memory read operations, commonly referred to as “read disturb” properties.
FIG. 1 illustrates a conventional single-ended SONOS memory array circuit 100 using a conventional sensing configuration for a memory read mode operation. The sensing configuration includes two stacks, one having memory cells referred to as matrix cell/SONOS cell 101 and the other having a reference current 102. The matrix cell 101 is part of the memory array and is located in the memory core. The reference current 102 is not part of the memory core and is placed near the sense amplifier (e.g., out of the memory array). In the read mode, the accessed SONOS cell pass gate is connected to a power supply Vpwr, while the un-accessed cell in the memory array pass gate is at ground. The reference current 102 is generated in such a way that its value is approximately half-way between the program cell current (Ipgm) and the erase cell current (Iers). The reference current 102 is compared against the accessed SONOS cell current to determine whether it is a program cell or erase cell.
Referring again to FIG. 1, the left stack includes a memory cell with its Bit line BL connected to a column decoder transistor N11 (107) whose gate is connected to column access transistor gate signal (Col). After passing through the column decoder transistor N11 (107), the bit line BL is connected to a source of a transistor N21 (106) whose gate is connected to a fixed biasing signal (Bias). The drain of transistor N21 (106) is connected to a load resistor RL1 (104). The transistor N21 (106) essentially forms a common gate amplifier with bit line BL as input signal and output taken at the node Vpgm/Vers. The right stack comprises the reference current 102 in the bottom of the stack. The bit line BL of reference current stack goes through a column decoder transistor N12 (108), and is connected to the input of a common gate amplifier transistor N22 (107) at its source terminal. The drain of transistor N22 (017) is connected to the load resistor RL2 (105) (which could be, for example, a current mirror load or MOS diode connected. load). The output of the right stack is taken at node Vref. Signals from the nodes Vpgm/Vers and Vref are compared using a comparator circuit 103.
To illustrate the circuit operation in empirical form for correctly sensing the erased and programmed states of matrix cell 101, considering a first case, wherein Vpgm/Vers=Vpgm when reading programmed cell, and a second case, wherein Vpgm/Vers=Vers when reading erase cell. The ideal condition would be Vref=(Vers+Vpgm)/2 for comparing the program cell accessed voltage Vpgm or erased cell accessed voltage Vers through the comparator 103. The read margin is defined as the voltage differential developed at the input of the comparator 103 when performing the read operation. The program read margin is defined as Vpgm−Vref, for example, the voltage differential developed at the input of comparator 103 while accessing the program matrix cell. The erase read margin is defined as Vers−Vref, for example, the voltage differential developed at the input of comparator 103 while accessing the erase matrix cell. Under the above condition, Vref>Vers with a comparator output (OUT)=1, when the erase matrix cell is accessed, and Vref<Vpgm with the comparator output (OUT)=0, when program matrix cell is accessed. The resistors RL1 (104) and RL2 (105) (or, for example, a current mirror load/MOS diode connected transistor load) are sized in accordance with the above condition. Therefore, the conventional sense margin during program and erase cell access is read margin=(Iers-Ipgm)/2, assuming an ideal Iref=(Iers+Ipgm)/2 (see, e.g., FIG. 4).
There are numerous limitations of the conventional memory array circuit 100. For example, the sense margin is limited to (Iers-Ipgm)/2, given an ideal reference current Iref takes a predetermined value, as in Iref=(Iers+Ipgm)/2. Thus, there is a loss of read margin either for reading logic 1 or logic 0. The reference current Iref needs to be adjusted after chip manufacturing to center its value between the program (Ipgm) and erase (Iers) cell current, thereby increasing the test time and creating a need for additional circuit area. In addition, the program/erase cycling of memory cells deteriorates the cell characteristics (known as oxide rupture), thereby changing the memory cell current and causing Iref≠(Iers+Ipgm)/2, and resulting in incorrect reads (due to the program or erase cell read margin loss). Furthermore, the charge stored in the floating gate of flash cells leaks as function of time, thereby drifting the ideal program/erase current of flash cells, and causing Iref≠(Iers+Ipgm)/2. Such a situation results in incorrect reads (due to either program or erase cell read margin loss).
Another limitation of the conventional memory circuits is that to get the double read margin it is required to store both data in the matrix cell (e.g., data “1” is stored as “Erase- Program” cell pair in order, whereas data “0” is stored as “Program-Erase” cell pair in order). However, doubling the read margin in such a manner requires a double area penalty, as at least two memory cells are required to store both data bits.